As is known in the art, cascode connected transistor circuit (FIG. 1A) includes a pair of transistors Q1, Q2 arranged as a two-stage amplifier, a common-source transconductance amplifier section formed by one of the transistors Q1 and followed by a common-gate current buffer amplifier section formed by the one of the second transistors Q2. Thus, the cascode is a dual gate device or circuit. A schematic diagram of one such arrangement is shown in FIG. 1A. Here, the transistors Q1, Q2 are Field Effect Transistors (FETs). It is noted that the transconductance amplifier section includes a common (grounded) source (S) FET Q1 having its gate electrode (GATE1) fed by an input signal. The current buffer amplifier section includes a common (grounded) gate (GATE2) FET Q2 having its gate connected to ground through a capacitor (C). The source (S) of the common (grounded) gate (S) FET Q2 and the drain (D) of the common source FET Q1 are connected together to provide a floating source/drain (S/D), as indicated. The amplified input signal is produced as an output signal at the drain (D) of FET Q2.
It is noted it that, in referring to FIG. 1B, a plan view layout of the cascode circuit in an MMIC structure is shown. It is first noted that the source (S) of Q1, the gate GATE 1 of Q1, the floating source/drain (S/D), the gate GATE 2 of Q2 and the drain D of Q2 are all on an active region, where a semiconductor mesa region is formed on the upper surface of the substrate. Thus, the gate GATE 1 of Q1 controls the flow of carriers passing through the active region between the source/drain (S/D) and the source (S) of FET Q1 and the gate of Q2 (GATE 2) controls the flow of carriers passing through the active region between the drain (D) of FET Q2 and the source/drain (S/D). The gate of FET Q1 (GATE 1) is fed by an input microwave transmission line, where, for example, a coplanar waveguide (CPW) transmission line having a center conductor disposed between a pair of ground plane conductors is disposed on an upper surface of a substrate. The center conductor is connected to a gate pad (GATE PAD 1) for GATE 1 of FET Q1. It is noted that the gate pad (GATE PAD 1) is off of (laterally displaced from) the active region. The gate GATE 2 of FET Q2 is connected to a gate pad (GATE PAD 2). It is noted is also noted that: (1) the gate pad (GATE PAD 2) is also off of (laterally displaced from) the active region and (2) both GATE PAD 1 and GATE PAD 2 are on the same side of the active region (here, in this layout, both GATE 1 and GATE 2 are on the left side of the active region). The drain (D) of the FET Q2 is connected to an output microwave transmission line, here also a CPW transmission line having a center conductor disposed between a pair of ground plane conductors. More particularly, the drain (D) is connected to the center conductor of the output CPW transmission line. The gate GATE 2 of FET Q2 is connected to a capacitor disposed on the upper surface of the substrate through the gate pad (GATE PAD 2), and air bridge conductor disposed over the GATE PAD 1 onto the upper plate of the capacitor. The lower plate of the capacitor is separated from the upper plate by a dielectric. The bottom plate is connected to a ground plane conductor of the output CPW transmission line. It is noted that the ground plane conductor of the input CPW and the output CPW may be connected to a ground plane (not shown) on the bottom surface of the substrate with conductive vias, not shown, passing vertically through the substrate.
Another cascode connected transistor circuit is shown in FIG. 2A and a plan view layout of the cascode circuit in an MMIC structure of FIG. 2A is shown in FIG. 2B. Here, the GATE PAD 2 is connected directly to ground and the source (S) is connected to ground through a capacitor.
The inventors have recognized that a long electrical path exits between the GATE 2 of FET Q2 and ground in both the layout of FIGS. 1B and 2B thereby increasing parasitic resistance and inductance on the gate's path to ground decreasing the circuits stability factor and thus effectively lowering Maximum Stable Gain (MSG). The inventors have recognized that this long electrical path exists because both gate pads (GATE PAD 1 and GATE PAD 2) are on the same side of the active region and thus a relatively long air bridge is required to “jump-over” or bridge the first gate pad (GATE PAD 1). This effect is particularly important in small, on the order of 50-nm gate length G-band FETs with both gates having the same lengths and a mesa 20 μm in width.
In accordance with the present disclosure, a cascode transistor circuit is provided having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the source and the floating source/drain and a second gate disposed between the floating source/drain and the drain. A first gate pad is displaced from the active region and is electrically connected to the first gate and a second gate pad is displaced from the active region and is electrically connected to the second gate. The first and the second gate pads are on opposite sides of the active region.
In one embodiment, a cascode transistor circuit is provided having: an input transmission line having a conductor disposed on an upper surface of a substrate; an output transmission line having a conductor disposed on the upper surface of the substrate; a first transistor having a gate electrode disposed on the upper surface of the substrate and connected to the conductor of the input transmission line, for controlling a flow of carriers, in a first portion of an active region of the substrate, between a source region of the substrate and a floating source/drain region of the substrate; a second transistor having a gate electrode disposed on the upper surface of the substrate for controlling a flow of carriers in an active region of the substrate between the floating source/drain region of the substrate and a drain region of the substrate, the drain region being connected to the conductor of the output transmission line; a first gate contact pad, laterally displaced from the active region, and connected to one end of the gate electrode of the first transistor, a second gate contact pad, laterally displaced from the active region, and connected to one end of the gate electrode of the second transistor. The first gate pad and the second gate pad are disposed on opposite sides of the active region. A capacitor is provided having: a lower plate disposed on the upper surface of the substrate; a dielectric disposed on the lower plate; and an upper plate disposed on the dielectric. One of the upper and lower plates is connected to either the source or second gate pad and the other one of the upper plate and lower plates is connected to the ground plane conductor portions of at least one of the input transmission line or the output transmission line.
In one embodiment, the lower plate is connected to either the source or second gate pad and the upper plate is connected is connected to the ground plane conductor portions of at least one of the input transmission line or the output transmission line.
In one embodiment, a cascode transistor circuit arrangement is provided having: a pair of laterally spaced cascode transistor circuits, each one having a corresponding one of a pair of active regions, each one of the pair of active regions being disposed on different portion of a surface of a substrate, each one of the active regions having a source, a drain, a floating source/drain, a first gate disposed between the source and the floating source/drain and a second gate disposed between the floating source/drain and the drain; a common gate pad connected to the first gate of both the cascode transistor circuits and displaced from the active region and between the pair of laterally spaced active regions; a first, second gate pad displaced from a first one of the active regions and electrically connected to the second gate of a first one of the pair of cascode connected transistors; a second, second gate pad displaced from a second one of the active regions and electrically connected to the second gate of a second one of the pair of cascode connected transistors. The common gate pad and the first, second gate pad are on opposite sides of the first one of the active regions and the common gate pad and the second, second gate pad are on opposite sides of the second one of the active regions.
In one embodiment, a common drain pad is connected to the drain of each one of the pair of cascode transistor circuits.
Thus the inventors have recognized that placing the gate pads on opposite sides of the active region simplifies the interconnect complexity. Further such an arrangement allows for parallel cascode devices to share a gate (RF input gate) connection and common drain (RF output) connection. The common connected gate (the ac grounded gate in the cascode) directly connects to the bottom plate of a capacitor that acts as AC ground. This is a major reduction in series inductance to ground versus the previous state-of-the-art which used a long air-bridge connection. A reduction in inductance to ground should increase maximum available gain of the dual gate at the desired frequency and contribute to greater device stability.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.